In the ongoing drive toward smaller, faster and cheaper chips implementing electronic circuits, the design and manufacturing fields are merging. Modem integrated circuit layout is often done automatically using electronic design automation (EDA) tools. EDA tools are a category of tools for designing and producing electronic systems ranging from printed circuit boards (PCBs) to integrated circuits. The term EDA is also used as an umbrella term for computer engineering, computer design and manufacturing of electronics, and the discipline of electrical engineering. EDA is divided into many, and sometimes overlapping, sub-areas. Those areas align with the path of manufacturing from design to mask generation.
As part of the manufacturing and design process of microchips, a designer must be able to design and modify a layout in such a way as to accomplish dual goals. The first goal relates to functionality and performance as well as meeting the requirements of the chip's usage. The second goal relates to manufacturing and laying out the shapes in such a way as to meet fabricator requirements for processing and optimum yield.
In order to achieve these goals, DFM tools have historically focused on meeting the second requirement. More specifically, such tools are used to modify a design of a circuit to make it easier to build in the wafer line, and to provide high yields during production. However, applying all manufacturing rules can often introduce variability in device performance. Thus, a designer needs to be cautious in applying DFM recommendations to performance-sensitive designs.
As technologies evolve and wafer dimensions continually decrease, more performance based rules are introduced. Performance based rules attempt to ensure that devices perform close to a predetermined standard, i.e., a model. However, in order to meet performance based rules, often other changes are made that may negatively impact manufacturability concerns such as yield and critical area.
In general, a designer knows that the circuit layout directly affects circuit performance and yield. It is also known that recommended design practices and rules for improving yield and performance are often in conflict due to space constraints. In the past, one solution included designing the recommendations to a middle ground, i.e., adopting a modified ground rule value without implementing the full DFM recommended value.
A problem with this approach is that there is no efficient manner of determining how critical a particular component, e.g., a Field Effect Transistor (FET), is to overall circuit performance. Thus, modifications may be introduced into a circuit without knowing all the facts. If a particular component is critical and any performance variation detrimental to the overall circuit performance, priority should be given to performance based rules. If the component is not critical in the logic flow, large variations may be tolerated with little or no impact to the end result. In the latter case, priority should be given to non-performance based rules.
Thus, it is desirable to provide a manner of identifying which circuits are critical, and what timing sensitivities exist so that a DFM reviewer or tool can adopt full DFM values for recommended rules on non-critical circuits, while maintaining tighter rules for critical performance based circuits.